LUT-Lock: A Novel LUT-based Logic Obfuscation for FPGA-Bitstream and ASIC-Hardware Protection

In this work, we propose LUT-Lock, a novel Look-Up-Table-based netlist\nobfuscation algorithm, for protecting the intellectual property that is mapped\nto an FPGA bitstream or an ASIC netlist. We, first, illustrate the\neffectiveness of several key features that make the LUT-based obfuscation more\nresilient against SAT attacks and then we embed the proposed key features into\nour proposed LUT-Lock algorithm. We illustrates that LUT-Lock maximizes the\nresiliency of the LUT-based obfuscation against SAT attacks by forcing a near\nexponential increase in the execution time of a SAT solver with respect to the\nnumber of obfuscated gates. Hence, by adopting LUT-Lock algorithm, SAT attack\nexecution time could be made unreasonably long by increasing the number of\nutilized LUTs.\n