Deployment of deep neural networks for applications that require very high\nthroughput or extremely low latency is a severe computational challenge,\nfurther exacerbated by inefficiencies in mapping the computation to hardware.\nWe present a novel method for designing neural network topologies that directly\nmap to a highly efficient FPGA implementation. By exploiting the equivalence of\nartificial neurons with quantized inputs/outputs and truth tables, we can train\nquantized neural networks that can be directly converted to a netlist of truth\ntables, and subsequently deployed as a highly pipelinable, massively parallel\nFPGA circuit. However, the neural network topology requires careful\nconsideration since the hardware cost of truth tables grows exponentially with\nneuron fan-in. To obtain smaller networks where the whole netlist can be\nplaced-and-routed onto a single FPGA, we derive a fan-in driven hardware cost\nmodel to guide topology design, and combine high sparsity with low-bit\nactivation quantization to limit the neuron fan-in. We evaluate our approach on\ntwo tasks with very high intrinsic throughput requirements in high-energy\nphysics and network intrusion detection. We show that the combination of\nsparsity and low-bit activation quantization results in high-speed circuits\nwith small logic depth and low LUT cost, demonstrating competitive accuracy\nwith less than 15 ns of inference latency and throughput in the hundreds of\nmillions of inferences per second.\n