A Deep Learning Framework for Verilog Autocompletion Towards Design and Verification Automation

Innovative Electronic Design Automation (EDA) solutions are crucial for meeting the design requirements of increasingly complex electronic devices. Verilog, a hardware description language, is widely used for the design and verification of digital circuits and is synthesized using specific EDA tools. However, writing code is a repetitive and time-intensive task. This paper proposes a deep learning framework for training a Verilog auto-completion model along with a dataset of Verilog code files and snippets from open-source repositories. The framework involves integrating models pretrained on general programming language data and finetuning them on a dataset curated to be similar to a target downstream task. This is validated by comparing different pretrained models trained on different subsets of the proposed Verilog dataset using multiple evaluation metrics. These experiments demonstrate that the proposed framework achieves better BLEU, ROUGE-L, and chrF scores by 9.5%, 6.7%, and 6.9%, respectively, compared to a model trained from scratch. This validates our framework, which has already inspired more recent related works.