Macro Placement by Wire-Mask-Guided Black-Box Optimization

Summary

This paper proposes a new black-box optimization framework, called WireMask-BBO, for macro placement, which is an important problem in the electronic design automation (EDA) community. By using different black-box optimization algorithms, The experiments show it can achieve improvements (shorter half-perimeter wirelength (HPWL)) over previous methods.

Strengths

The general framework WireMask-BBO proposed by this paper somewhat provides new angle for macro placement problem. The paper is well-written and it is easy to follow.

Weaknesses

The scalability of the proposed method is doubtful because Bayesian optimization and evolutionary algorithm may not be suitable for large-scale problems. The experiments are insufficient. The experiments don’t compare with the state-of-the-art macro placement method. The experiments don’t compare the runtime of the proposed method with other methods.

Questions

(1) How about the performance comparison with the state-of-the-art macro placement method in the experiments? (2) How about the runtime of the proposed method and compare it with other methods? (3) Is it necessary to tune hyperparameters extensively to achieve good results in the experiments?

Rating

5: Borderline accept: Technically solid paper where reasons to accept outweigh reasons to reject, e.g., limited evaluation. Please use sparingly.

Confidence

4: You are confident in your assessment, but not absolutely certain. It is unlikely, but not impossible, that you did not understand some parts of the submission or that you are unfamiliar with some pieces of related work.

Soundness

2 fair

Presentation

2 fair

Contribution

2 fair

Limitations

Yes

Summary

This paper presents a framework using BBO for macro placement in VLSI designs. Any placement solution for a set of macros can be optimized using the wire masks (presented in a prior work using RL) where the optimization goal is to minimize the HPWL of the output. In addition to random inputs, the framework can also be used for further enhancement of any existing solutions.

Strengths

The work tackles a critical problem in VLSI designs. The idea of casting the placement problem to a BBO is interesting and novel. This framework can be used to further improve any existing solutions for the macros. This can be used as another step in PnR with reasonable runtime. Overall, the paper explains the problem, the existing solutions, and the proposed work clearly.

Weaknesses

The idea of casting the placement problem to a BBO is interesting and novel. However, as the authors admit in Section 1 that this work does not develop any new BBO algorithm. To the reviewer, the experimental results are not extensive and convincing; this is described in the limitation section. The paper also states in the conclusion that it can only place macros but not standard cells without explanation, which limits the application of the proposed work to the actual VLSI problem. On the other hand, this framework can be used to further improve any existing solutions for the macros. This can be used as another step in PnR with reasonable runtime.

Questions

Why is EA-based framework better than the other two BBO algorithms? Why cannot the proposed framework used for standard cell placement? Can't you use a more fine-grained canvas for the problem, where the standard cells are larger than the grid size?

Rating

5: Borderline accept: Technically solid paper where reasons to accept outweigh reasons to reject, e.g., limited evaluation. Please use sparingly.

Confidence

4: You are confident in your assessment, but not absolutely certain. It is unlikely, but not impossible, that you did not understand some parts of the submission or that you are unfamiliar with some pieces of related work.

Soundness

2 fair

Presentation

3 good

Contribution

2 fair

Limitations

The computational time for the proposed work seems to be high. Therefore, in the experimental section, the paper does not include the complex benchmark that has thousands of macros to be placed. This contradicts with the claim the paper that this approach is scalable. The evaluation of the proposed method only uses 5 random seeds. It would be more convincing if the paper includes more experimental data. The proposed framework cannot place the standard cells in the design. Therefore, the comparison between this work and the existing methods seems to be unfair.

Summary

The authors propose a new placement method that is based on the black-box framework. The framework leverages the wire mask-guided information and can achieve significant placement results compared with the state-of-the-art methods.

Strengths

1. The novel method is based on black-box optimization, which has not been implemented on the placement task before. Although many RL methods have been proposed, they are not very efficient enough. Black-box optimization might be a viable direction. 2. The wire mask as the guide for generating phenotype representation is also very novel. It can quickly render a suitable solution based on the initial representation, improving efficiency. 3. The experiments are very comprehensive and solid, showing that the performance of the proposed method can consistently outperform existing methods. 4. The paper writing is well-written and easy to understand. 5. The code is open-source, improving reproducibility.

Weaknesses

1. The full placement cannot surpass the DREAMPlace, which means the proposed method can only work well in macro placement. 2. The reasons for the improvement in the congestion metric are not clear. The method does not consider the congestion metric in its search process. 3. The recent work [1] based on Maskplace should also be discussed in the related work part. [1] Lai Y, Liu J, Tang Z, et al. Chipformer: Transferable chip placement via offline decision transformer.

Questions

1. Have you tested the effect of the number of initial states on the final results? 2. Why your method can get better congestion results when you do not consider it in your method. 3. The efficient comparison only provides the clock time. However, the number of search steps is also substantial. Could you provide how many steps you use for each circuit (or how much clock time is consumed to perform a step)?

Rating

7: Accept: Technically solid paper, with high impact on at least one sub-area, or moderate-to-high impact on more than one areas, with good-to-excellent evaluation, resources, reproducibility, and no unaddressed ethical considerations.

Confidence

5: You are absolutely certain about your assessment. You are very familiar with the related work and checked the math/other details carefully.

Soundness

3 good

Presentation

3 good

Contribution

3 good

Limitations

Yes.

Summary

This paper proposes a novel black-box optimization (BBO) framework, namely WireMask-BBO, for macro placement in chip design. Specifically, it devises a post-processing technique that legalizes any searched placement solution while optimizing the half-perimeter wirelength (HPWL). The post-processing technique allows us to perform BBO algorithms to search for solutions with better HPWL. Experiments demonstrate that WireMask-BBO outperforms previous state-of-the-art (SOTA) methods, achieving better HPWL performance in less time.

Strengths

1. This paper explores BBO methods for macro placement, which may provide a new insight for the research community. 2. The proposed post-processing technique is simple yet effective. It also has a good versatility because it can be combined with other placement methods and BBO methods.

Weaknesses

1. The propose of the post-processing is purely heuristic. The motivation is unclear and intuitive explanation for the advances is insufficient. 2. The proposed method only targets on optimizing HPWL, without explicitly considering other important metrics like routing wirelength or congestion. It does not consider cells and routing either. Moreover, the framework can be hardly transferred to tasks with those metrics under consideration, which limits its real application in EDA. 3. Because introducing BBO-based methods is one of the core contributions of this paper, the authors may want to illustrate the implementation of BBO algorithms for macro placement more detailly. 4. In Algorithm 1, the macros are ordered decreasingly according to areas, while in Figure 3, the smaller macro-A is considered first. 5. A recent related work [1] is missing. [1] Lai Y, Liu J, Tang Z, et al. Chipformer: Transferable chip placement via offline decision transformer. ICML 2023.

Questions

1. Since only HPWL is considered as the objective, why does WireMask-BBO also outperforms MaskPlace in congestion? 2. What are the results of routing wirelengths? 3. Under this framework, how to take cell placement or some important yet computationally insufficient metrics into consideration?

Rating

6: Weak Accept: Technically solid, moderate-to-high impact paper, with no major concerns with respect to evaluation, resources, reproducibility, ethical considerations.

Confidence

4: You are confident in your assessment, but not absolutely certain. It is unlikely, but not impossible, that you did not understand some parts of the submission or that you are unfamiliar with some pieces of related work.

Soundness

3 good

Presentation

3 good

Contribution

3 good

Limitations

N/A

Thank you. Increase my score to 6.

I appreciate the authors' efforts in responding to my questions. I hope the authors will revise the paper accordingly. Though there are still some limitaions as we have discussed, I think the proposed framework will benefit the research community, and it deserves further study. I have raised my score from 5 to 6.