Circuit as Set of Points

Summary

This paper introduces a novel perspective on circuit design by treating circuit components as point clouds and utilizing point cloud perception methods for feature extraction. Previous approaches either relied on hand-crafted methods to transform circuit designs into images for CNN feature extraction or employed GNNs for graph-based feature extraction, which required time-consuming preprocessing. In contrast, the proposed method enables direct feature extraction from raw data without preprocessing, allowing for end-to-end training and achieving high performance. Experimental results on the CircuitNet dataset demonstrate the superiority of the proposed method in congestion prediction and design rule check (DRC) violation prediction tasks. This approach establishes a connection between point cloud perception methods and EDA algorithms, facilitating the application of collective intelligence in solving circuit design tasks. The method outperforms hand-crafted features and CNN-based methods in feature extraction while eliminating the need for preprocessing, thereby reducing processing time. The work shows potential as a universal feature extractor for chip design, adaptable to a wide range of downstream tasks.

Strengths

The paper introduces a groundbreaking method that addresses circuit congestion prediction and design rule check (DRC) violation prediction in electronic design automation (EDA). By leveraging the concept of point clouds and incorporating a genetic algorithm (GA) module, the proposed approach achieves significant improvements over existing techniques commonly employed in EDA tools. The utilization of point cloud perception enables a fresh perspective on circuit design analysis, allowing for more accurate and efficient prediction of congestion and violations. Additionally, the integration of the GA module enhances the optimization process, leading to enhanced results and performance. This novel method showcases the potential for innovative approaches in EDA, opening doors to advanced techniques that can better handle circuit design challenges and contribute to improved circuit performance and reliability.

Weaknesses

To enhance the comprehensiveness of the paper, it would be valuable to expand the evaluation to encompass other applications within the domain of electronic design automation (EDA), such as circuit placement. By investigating the effectiveness of the proposed method in various EDA tasks, including placement, the authors can provide a more holistic understanding of its capabilities and potential impact. Furthermore, conducting additional ablation studies that delve into the runtime and scaling model trade-offs would contribute to a deeper analysis of the proposed approach. These studies would shed light on the performance and efficiency aspects of the method, allowing for a better understanding of its behavior under different conditions and dataset sizes. This information would be particularly useful for practitioners and researchers aiming to apply the method in real-world scenarios. Another aspect worth exploring is the authors' emphasis on the encoder while leaving the decoder section with limited analysis. This raises intriguing questions regarding the possibility of modifying the output format to potentially improve the EDA software pipeline. Investigating alternative output formats or exploring ways to optimize the decoder component could uncover opportunities for further enhancing the proposed method's integration into EDA workflows. Moreover, the paper opens up avenues for considering the incorporation of this approach into other areas of EDA tools beyond congestion prediction and DRC violation prediction. Exploring how the proposed method could be leveraged in other stages of the EDA process, such as routing, power optimization, or physical design verification, would demonstrate its versatility and potential for broader application. This could foster innovation in multiple facets of EDA, leading to more efficient and advanced chip designs. By addressing these suggestions, the paper would offer a more comprehensive evaluation, deeper insights into runtime and scaling trade-offs, considerations for optimizing the decoder section, and opportunities for applying the proposed approach in various EDA tool domains. These extensions would further solidify the paper's contribution and provide valuable guidance for future research and development in the EDA field.

Questions

A few questions: In figure 5 shows, 3x model size than unet. Which creates the question of scaling model. If a smaller version of the model with same size of Unet will get better accuracy? In figure 4 shows preprocessing times, what is the total runtime and inference time of the model?

Rating

7: Accept: Technically solid paper, with high impact on at least one sub-area, or moderate-to-high impact on more than one areas, with good-to-excellent evaluation, resources, reproducibility, and no unaddressed ethical considerations.

Confidence

3: You are fairly confident in your assessment. It is possible that you did not understand some parts of the submission or that you are unfamiliar with some pieces of related work. Math/other details were not carefully checked.

Soundness

3 good

Presentation

2 fair

Contribution

3 good

Limitations

The authors addressed the limitations correctly.

Summary

This paper proposes to use point cloud perception methods to extract features from the circuit by treating the circuit components as point clouds. The proposed method solves the infeasibility of end-to-end training in the CNN-based method and the limitation of time-consuming preprocessing in the GNN-based method. The evaluation result shows the effectiveness of the proposed method on CircuitNet dataset: it outperforms the mainstream CNN-based and GNN-based methods on congestion prediction and design rule check violation prediction.

Strengths

1. This paper facilitates Electronic Design Automation (EDA) by using the well-researched point cloud perception methods, providing a new perspective for circuit design. 2. The encoder part, especially the multi-scale grid-based attention architecture, reduces the computational complexity, and compresses the information as well.

Weaknesses

1. Please give the runtime latency comparison with the CNN-based method to prove the proposed method reduces design cycles.

Questions

1. In the decoder part, motivations for using ResNet18 and UNet++ are missing. Is the selection of network architecture in the decoder part based on the downstream tasks? For different tasks, is necessary to use different networks?

Rating

6: Weak Accept: Technically solid, moderate-to-high impact paper, with no major concerns with respect to evaluation, resources, reproducibility, ethical considerations.

Confidence

2: You are willing to defend your assessment, but it is quite likely that you did not understand the central parts of the submission or that you are unfamiliar with some pieces of related work. Math/other details were not carefully checked.

Soundness

3 good

Presentation

3 good

Contribution

2 fair

Limitations

The authors addressed limitations.

Summary

This paper proposes a new perspective on circuit design by viewing circuit components as point clouds and using point cloud perception methods to extract features from circuits. This achieves the goals of directly extracting features from raw data, end-to-end training, and high performance. Experimental results show that the method achieves state-of-the-art performance on congestion prediction and design rule checking tasks.

Strengths

a. Overall summary: The authors propose a novel approach for chip design and manufacturing processes using Electronic Design Automation (EDA) algorithms and tools. b. Methods: The authors treat circuit components as point clouds and use point cloud perception methods for feature extraction. They utilize a grid-based attention (GA) module to aggregate multi-scale and global geometric information. The encoder converts point-wise features to grid-wise features and generates grid-wise features using a scatter-sum operator. The decoder refines and downsamples the features extracted by the encoder using a ResNet-18 backbone and a UNet++ segmentation head. The loss function incorporates label distribution smoothing to address imbalanced classification problems. c. Experimental results: The authors conducted experiments on the CircuitNet dataset. The proposed method achieved state-of-the-art performance in congestion prediction and design rule check (DRC) violation prediction tasks. The method outperformed UNet in terms of performance, with a runtime memory of 3721MB for the proposed method and 1931MB for UNet.

Weaknesses

N/A

Questions

N/A

Rating

6: Weak Accept: Technically solid, moderate-to-high impact paper, with no major concerns with respect to evaluation, resources, reproducibility, ethical considerations.

Confidence

4: You are confident in your assessment, but not absolutely certain. It is unlikely, but not impossible, that you did not understand some parts of the submission or that you are unfamiliar with some pieces of related work.

Soundness

3 good

Presentation

3 good

Contribution

3 good

Limitations

The limitations is not explicitly discussed, but the future work has plotted the current limitation and proposed the next direction that authors will try to tackle such limitation. No negative societal impact

Summary

The manuscript presents several claims. Firstly, it introduces a novel perspective on "point cloud perception methods" for performing EDA tasks. By treating circuit components as point clouds and utilizing point cloud perception networks, the paper proposes an innovative approach to solving these tasks. Secondly, it claims superiority over CNN and GNN-based methods commonly used for EDA tasks. The authors assert that their method outperforms these existing techniques. Thirdly, the paper positions itself as the state-of-the-art solution for EDA tasks. The experimental section is well-written, easy to understand, and the overall presentation flow of the manuscript is good.

Strengths

In terms of originality, paper uses novel perspective on the solving the EDA problems which novelty in the paper. clear description of the method, and well-structured experimental section, which includes an ablation study to enhance the validity

Weaknesses

The experimental results provided in the paper are not sufficient. For instance, Table1 shows the comparison of congestion with CNN and GNN methods. However, in case of CNN the cited paper uses ISPD2015 dataset (Open source in circuitnet), while this paper uses circuitnet. It may be better first show comparison with Circuitnet paper https://www.sciengine.com/SCIS/doi/10.1007/s11432-022-3571-8 Similarly, CircuitGNN[39] which uses the ISPD2011 dataset while this paper uses Circuitnet dataset. Maybe add another comparison point cloud perception methods vs CircuitGNN on ISPD 2011 dataset.

Questions

1. Add more comparison SOTA GNN & CNN based method comparisons for both congestion and DRC violation prediction 2. Show results on other open-source datasets like (ISPD2015 which is available in circuitnet with grid level labels) and DAC 2012. 3. The paper mentions “performance is higher without excessive GPU memory” but the memory required here is approximately double that Unet. If authors could show the comparison of memories size of graph and memory required by your method and SOTA methods would be fair. 4. The paper mentions that “novel perspective on circuit design” and “work has the potential to serve as a universal feature extractor for chip design” But only showed two tasks. To make these claim needs to perform other tasks in circuit design like power prediction, and delay prediction.

Rating

4: Borderline reject: Technically solid paper where reasons to reject, e.g., limited evaluation, outweigh reasons to accept, e.g., good evaluation. Please use sparingly.

Confidence

4: You are confident in your assessment, but not absolutely certain. It is unlikely, but not impossible, that you did not understand some parts of the submission or that you are unfamiliar with some pieces of related work.

Soundness

3 good

Presentation

3 good

Contribution

2 fair

Limitations

• The scope of idea is may be limited by the size of the graph. For example, if the graph contains millions of nodes and edges which requires large GPU memory to process. • Generalization of the method presented in paper is explored it might be the limitation since it only works on grid-based dataset. But GNN is more generalized to solve EDA problems since netlist is a graph.

thanks for clarification

thanks for clarification and for acknowledging the points.