The rapid advancement of neural network applications necessitates hardware that not only accelerates computation but also adapts efficiently to dynamic processing requirements. While processing-in-pixel has emerged as a promising solution to overcome the bottlenecks of traditional architectures at the extreme-edge, existing implementations face limitations in reconfigurability and scalability due to their static nature and inefficient area usage. Addressing these challenges, we present a novel architecture that significantly enhances the capabilities of processing-in-pixel for convolutional neural networks (CNNs). Our design innovatively integrates nonvolatile memory (NVM) with novel unit pixel circuit design, enabling dynamic reconfiguration of synaptic weights, kernel size, channel size, and stride size; thus, offering unprecedented flexibility and adaptability. By using a separate die for the pixel circuit and storing synaptic weights, our circuit achieves a substantial reduction in the required area per pixel, thereby increasing the density and scalability of the pixel array. Simulation results demonstrate dot product operations of the circuit, the nonlinearity of its analog output and a novel bucket-select curvefit model is proposed to capture it. This work not only addresses the limitations of current in-pixel computing approaches but also opens new avenues for developing more efficient, flexible, and scalable neural network hardware, paving the way for advanced artificial intelligence (AI) applications.