The paper addresses advancements in Generative Artificial Intelligence\n(GenAI) and digital chip design, highlighting the integration of Large Language\nModels (LLMs) in automating hardware description and design. LLMs, known for\ngenerating human-like content, are now being explored for creating hardware\ndescription languages (HDLs) like Verilog from natural language inputs. This\napproach aims to enhance productivity and reduce costs in VLSI system design.\nThe study introduces "AiEDA", a proposed agentic design flow framework for\ndigital ASIC systems, leveraging autonomous AI agents to manage complex design\ntasks. AiEDA is designed to streamline the transition from conceptual design to\nGDSII layout using an open-source toolchain. The framework is demonstrated\nthrough the design of an ultra-low-power digital ASIC for KeyWord Spotting\n(KWS). The use of agentic AI workflows promises to improve design efficiency by\nautomating the integration of multiple design tools, thereby accelerating the\ndevelopment process and addressing the complexities of hardware design.\n