CMOS Implementation of Field Programmable Spiking Neural Network for Hardware Reservoir Computing

The increasing complexity and energy demands of large-scale neural networks, such as deep neural networks and large language models, challenge their practical deployment in edge applications due to high power consumption, area requirements, and privacy concerns. Spiking neural networks, particularly in analog implementations, offer a promising low-power alternative but suffer from noise sensitivity and connectivity limitations. This work presents a novel CMOS-fabricated field-programmable neural network architecture for hardware reservoir computing (RC). We propose a leaky integrate-and-fire neuron circuit featuring integrated voltage-controlled oscillators and synaptic weights programmed via an on-chip field-programmable gate array framework. This framework enables direct connectivity between neurons, supporting the implementation of arbitrary reservoir configurations. The performance of the system is validated through simulation and chip measurements, demonstrating effective FORCE algorithm learning alongside competitive results in linear/non-linear memory capacity and NARMA10 benchmarks. The neuron design achieves compact area utilization (around 540 NAND2-equivalent units) and low energy consumption (21.7 pJ/pulse) without requiring ADCs for information readout, making it ideal for system-on-chip integration of RC. This architecture paves the way for scalable, energy-efficient neuromorphic systems capable of performing real-time learning and inference with high configurability and digital interfacing.