Spatial accelerators, composed of arrays of compute-memory integrated units, offer an attractive platform for deploying inference workloads with low latency and low energy consumption. However, fully exploiting their architectural advantages typically requires careful, expert-driven mapping of computational graphs to distributed processing elements. In this work, we automate this process by framing the mapping challenge as a black-box optimization problem. We introduce the first evolutionary, hardware-in-the-loop mapping framework for neuromorphic accelerators, enabling users without deep hardware knowledge to deploy workloads more efficiently. On Intel's Loihi 2, our method achieves up to 35% reduction in total latency compared to default heuristics on two sparse multilayer perceptron networks. We further demonstrate the scalability of our approach to multi-chip systems and observe an up to 40% gain in energy efficiency, without explicitly optimizing for it.