Bio-inspired neuromorphic hardware is an emerging computing architecture, which features highly parallel and distributed computing elements similar to the functionality of human brain. Recent study shows that neuromorphic hardware can achieve state-of-the-art performance in various cognitive tasks. However, limitations in fabrication technology has led to limitations in fan-in, fan-out, memory capacity, connectivity etc., making neuromorphic chips difficult to program. Neural networks have to satisfy specific constraints in order to be mapped to hardware, which not only requires developers to have knowledge of specific hardware, but also makes training difficult. We proposed a general framework to address above issues. It consists of a workflow to convert an existing neural network to satisfy the hardware constrains while minimizing the error caused by conversion, algorithms to increase hardware resource utilization and minimize on-chip communication cost are also proposed and evaluated. The experimental results show that the framework reduces conversion error to 0.67%, and reduces 53% of communication latency.
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A General Framework to Map Neural Networks onto Neuromorphic Processor
Semantic Scholar · Computer Science · 2019
Abstract
Bio-inspired neuromorphic hardware is an emerging computing architecture, which features highly parallel and distributed computing elements similar to the functionality of human brain. Recent study shows that neuromorphic hardware can achieve state-of-the-art performance in various cognitive tasks. However, limitations in fabrication technology has led to limitations in fan-in, fan-out, memory capacity, connectivity etc., making neuromorphic chips difficult to program. Neural networks have to satisfy specific constraints in order to be mapped to hardware, which not only requires developers to have knowledge of specific hardware, but also makes training difficult. We proposed a general framework to address above issues. It consists of a workflow to convert an existing neural network to satisfy the hardware constrains while minimizing the error caused by conversion, algorithms to increase hardware resource utilization and minimize on-chip communication cost are also proposed and evaluated. The experimental results show that the framework reduces conversion error to 0.67%, and reduces 53% of communication latency.