A Novel Reconfigurable Hardware Architecture of Neural Network

Neural networks have been commonly used in learning applications. Implementing a neural network on hardware is a complex and challenging task for hardware designers as many hyperparameters and trade-offs need to be considered. This paper presents a reconfigurable feed-forward neural network which can be used for different applications. The proposed method has the flexibility to change the node organization to be suitable for an application. The network is divided into two parts: one part has a fixed node in each layer and the second part includes the reconfigurable nodes. The reconfigurable nodes have the ability to switch from one layer to another to speed up the network. The proposed method is compared with the traditional network, and the result shows the proposed method improves the performance of the network. The learning speed is improved by 35% using 100 neurons within a layer. The hardware implementation of the proposed method is presented using VHDL and Altera Arria10 GX FPGA.

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A Novel Reconfigurable Hardware Architecture of Neural Network

Semantic Scholar · Computer Science · 2019

Abstract

Neural networks have been commonly used in learning applications. Implementing a neural network on hardware is a complex and challenging task for hardware designers as many hyperparameters and trade-offs need to be considered. This paper presents a reconfigurable feed-forward neural network which can be used for different applications. The proposed method has the flexibility to change the node organization to be suitable for an application. The network is divided into two parts: one part has a fixed node in each layer and the second part includes the reconfigurable nodes. The reconfigurable nodes have the ability to switch from one layer to another to speed up the network. The proposed method is compared with the traditional network, and the result shows the proposed method improves the performance of the network. The learning speed is improved by 35% using 100 neurons within a layer. The hardware implementation of the proposed method is presented using VHDL and Altera Arria10 GX FPGA.

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