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Network-On-Chip Based Test Access Mechanism for Multi-Site Test

In this paper, we introduce a method to significantly increase the number of semiconductor devices tested simultaneously in the package test stage using an NOC interconnect structure. As the NOC implemented on the interface board between the ATE and the DUT can increase the number of DUTs freely, test parallelism improves dramatically. Furthermore, the NOC-based test access method can upgrade the efficiency of channel usage as well as test parallelism through packet-type transmission. Experimental results show that the test time reduces in proportion to the number of connected DUTs.

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Network-On-Chip Based Test Access Mechanism for Multi-Site Test

Semantic Scholar · Engineering · 2018

Abstract

In this paper, we introduce a method to significantly increase the number of semiconductor devices tested simultaneously in the package test stage using an NOC interconnect structure. As the NOC implemented on the interface board between the ATE and the DUT can increase the number of DUTs freely, test parallelism improves dramatically. Furthermore, the NOC-based test access method can upgrade the efficiency of channel usage as well as test parallelism through packet-type transmission. Experimental results show that the test time reduces in proportion to the number of connected DUTs.

Source of record · Semantic Scholar

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