In this paper, we present a method to efficiently detect the edge of an image by using hardware. Canny edge detection algorithm which is strong against. However it has a disadvantage that the processing speed is slower than other detection methods. Sobel detector can be implemented in hardware with less memory and faster than Canny edge detector. In software, each result is stored in the memory, but hardware uses line buffers to reduce memory size and increase speed. The length of the line buffer is equal to the size of the vertical pixels of the image. To implement in hardware, we use Verilog HDL and the function of the HDL code was verified by a FPGA board and a monitor. Using our method, full HD video can be processed up to 48 frames per second, and the size of the memory can be reduced to 33 percent of the conventional method.
Paper
Full text
Design of Real-Time Hardware for Edge Detection
Semantic Scholar · Computer Science · 2018
Abstract
In this paper, we present a method to efficiently detect the edge of an image by using hardware. Canny edge detection algorithm which is strong against. However it has a disadvantage that the processing speed is slower than other detection methods. Sobel detector can be implemented in hardware with less memory and faster than Canny edge detector. In software, each result is stored in the memory, but hardware uses line buffers to reduce memory size and increase speed. The length of the line buffer is equal to the size of the vertical pixels of the image. To implement in hardware, we use Verilog HDL and the function of the HDL code was verified by a FPGA board and a monitor. Using our method, full HD video can be processed up to 48 frames per second, and the size of the memory can be reduced to 33 percent of the conventional method.