Scaling of Split-Gate Flash Memory for Embedded Controllers and Machine Learning Applications
Scaling prospects and challenges of the embedded split-gate SuperFlash®(ESF) memory technology to 28 nm and smaller process nodes are presented. We further propose a novel process integration scheme to build SuperFlash® memory with a 14nm process node. On-going scaling and optimization of ESF memory technology continues to enable new applications such as machine learning in which an ESF memory array is used to implement vector-matrix multiplications for neural networks. To demonstrate this use case, the capability and performance of 40 and 28 nm split-gate SuperFlash® cells in low-power sub-threshold region is presented.
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Scaling of Split-Gate Flash Memory for Embedded Controllers and Machine Learning Applications
Semantic Scholar · Computer Science · 2020
Abstract
Scaling prospects and challenges of the embedded split-gate SuperFlash®(ESF) memory technology to 28 nm and smaller process nodes are presented. We further propose a novel process integration scheme to build SuperFlash® memory with a 14nm process node. On-going scaling and optimization of ESF memory technology continues to enable new applications such as machine learning in which an ESF memory array is used to implement vector-matrix multiplications for neural networks. To demonstrate this use case, the capability and performance of 40 and 28 nm split-gate SuperFlash® cells in low-power sub-threshold region is presented.