Variation-Aware Test for Logic Interconnects using Neural Networks – A Case Study

Abstract

In today’s system-on-chips, interconnects increasingly affect the reliability of the system. Crosstalk defects can result in delay and glitch faults and also aggravate aging mechanisms such as electro-migration. Furthermore, fab-induced deviations of the interconnect layout may lead to a reduced line spacing and enlarged crosstalk defects. While crosstalk testing at the system level directly measures the behavior of the interconnect section under test, at the logic level crosstalk effects may interfere with delay faults or parameter variations in the logic components. In particular, detecting gate-level crosstalk defects in the presence of parameter variations is a very challenging, yet very important task. In this work a method to distinguish between crosstalk-induced delays and parameter variations is presented. It is based on delay maps obtained from testing at multiple operating points. These delays maps can be classified into crosstalk-induced and variation-induced delay maps using an artificial neural network with a high success rate. Furthermore, it is shown how the basic classification scheme can be tuned to the practical constraints of interconnect testing.