Spiking-HDC: A Spiking Neural Network Processor with HDC Classifier Enabling Transfer Learning
This work proposes Spiking-HDC, a spiking neural network (SNN) processing system with hyperdimensional computing (HDC) and its hardware design for domain transfer scenarios. The input data is firstly fed into a two-layer SNN, serving as a feature extractor. It is followed by a HDC classifier to process feature vectors using hypervectors in binary representation. Such a system leverages HDC’s capability of single-pass learning, which can be adopted to rapidly updating but highly similar tasks by fine-tuning the HDC classifier with limited labeled data. By our experiments, the proposed system demonstrates transfer learning accuracy of 94.76%, 87.12% and 94.37% with few-shot samples on N-MNIST, DVS-Gesture and MNIST datasets, respectively. To apply Spiking-HDC model to extreme edge inference tasks, a dedicated processor is designed and implemented. The simulated results in 40 nm CMOS process illustrate that it has 0.88 mm2 core area and 1.8 mW power at 100 MHz frequency. In comparison to similar works, it achieves 3.8×-36× inference energy efficiency enhancement.
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Spiking-HDC: A Spiking Neural Network Processor with HDC Classifier Enabling Transfer Learning
Semantic Scholar · Computer Science · 2024
Abstract
This work proposes Spiking-HDC, a spiking neural network (SNN) processing system with hyperdimensional computing (HDC) and its hardware design for domain transfer scenarios. The input data is firstly fed into a two-layer SNN, serving as a feature extractor. It is followed by a HDC classifier to process feature vectors using hypervectors in binary representation. Such a system leverages HDC’s capability of single-pass learning, which can be adopted to rapidly updating but highly similar tasks by fine-tuning the HDC classifier with limited labeled data. By our experiments, the proposed system demonstrates transfer learning accuracy of 94.76%, 87.12% and 94.37% with few-shot samples on N-MNIST, DVS-Gesture and MNIST datasets, respectively. To apply Spiking-HDC model to extreme edge inference tasks, a dedicated processor is designed and implemented. The simulated results in 40 nm CMOS process illustrate that it has 0.88 mm2 core area and 1.8 mW power at 100 MHz frequency. In comparison to similar works, it achieves 3.8×-36× inference energy efficiency enhancement.