Design of Power-Efficient and Reliable SoC-SiP Architectures for Next-Generation AI Edge Systems
Even though significant progress has been achieved in SoC and SiP technology, remarkable weaknesses have been identified in power efficiency, thermal reliability, and on-chip interconnect scalability regarding the integration of artificial intelligence accelerators, heterogeneous chiplets, RF components, MEMS components, and high-speed memory solutions in present High-Performance Computing(HPC) design of the edge device domain. Using existing methods of designing SiPs, not only is the connectivity but also their reliability during long usage periods a concern, regarding the power consumption of systems like in-vehicle infotainment systems and other applications associated with various digital society services. A heterogeneous SoC-SiP architecture is proposed to realize adaptive VFS, WC memory orchestration, RC interconnect, across the realm of digital, analog, as well as Artificial Intelligence (AI) domains to deal with the mentioned problems. It is achieved through dynamic performance, power, as well as thermal management through modeling, chiplet-based packaging constraints, as well as monitor-based management. Through the utilization of lightweight machine learning predictor components in the consideration of power-thermal behavior along with reliability degradation, the proposed approach utilizes cross-layer co-optimization, facilitating the control of the location of both computation as well as data transfers, both intra chip as well as inter SiP connections. Through experimental evaluation results, it is evident that the power consumption of such an architecture is minimized by up to 32%, while reliability with respect to temperature improves by up to 28%, and the communication latency is improved by 21% with the same level of speed as compared to state-of-theart designs based on traditional AI-enabled SoC platforms. This infers that the presented proposal would be able to create the path for future scalable and trusted next-gen platforms for embedded HPC systems with the aid of AI, forming the building blocks for future societies to be created by information and communications systems.
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Design of Power-Efficient and Reliable SoC-SiP Architectures for Next-Generation AI Edge Systems
Semantic Scholar · 2026
Abstract
Even though significant progress has been achieved in SoC and SiP technology, remarkable weaknesses have been identified in power efficiency, thermal reliability, and on-chip interconnect scalability regarding the integration of artificial intelligence accelerators, heterogeneous chiplets, RF components, MEMS components, and high-speed memory solutions in present High-Performance Computing(HPC) design of the edge device domain. Using existing methods of designing SiPs, not only is the connectivity but also their reliability during long usage periods a concern, regarding the power consumption of systems like in-vehicle infotainment systems and other applications associated with various digital society services. A heterogeneous SoC-SiP architecture is proposed to realize adaptive VFS, WC memory orchestration, RC interconnect, across the realm of digital, analog, as well as Artificial Intelligence (AI) domains to deal with the mentioned problems. It is achieved through dynamic performance, power, as well as thermal management through modeling, chiplet-based packaging constraints, as well as monitor-based management. Through the utilization of lightweight machine learning predictor components in the consideration of power-thermal behavior along with reliability degradation, the proposed approach utilizes cross-layer co-optimization, facilitating the control of the location of both computation as well as data transfers, both intra chip as well as inter SiP connections. Through experimental evaluation results, it is evident that the power consumption of such an architecture is minimized by up to 32%, while reliability with respect to temperature improves by up to 28%, and the communication latency is improved by 21% with the same level of speed as compared to state-of-theart designs based on traditional AI-enabled SoC platforms. This infers that the presented proposal would be able to create the path for future scalable and trusted next-gen platforms for embedded HPC systems with the aid of AI, forming the building blocks for future societies to be created by information and communications systems.