SHADOW TAG MEMORY TO MONITOR STATE OF CACHELINES AT DIFFERENT CACHE LEVEL

A processing system includes a plurality of processor cores and a plurality of private caches. Each private cache is associated with a corresponding processor core of the plurality of processor cores and includes a corresponding first set of cachelines. The processing system further includes a shared cache shared by the plurality of processor cores. The shared cache includes a second set of cachelines, and a shadow tag memory including a plurality of entries, each entry storing state information for a corresponding cacheline of the first set of cachelines of one of the private caches.