MEMORY UNIT FOR DATA MEMORY REFERENCES OF MULTI-THREADED PROCESSOR WITH INTERLEAVED INTER-THREAD PIPELINE IN EMULATED SHARED MEMORY ARCHITECTURES

A memory unit for handling data memory references of a multi-threaded processor with interleaved inter-thread pipeline in emulated shared memory architectures, includes a step cache defining associative cache memory array where data stays valid till the end of ongoing step of multithreaded execution, the memory array incorporating a plurality of cache lines with data fields, each line containing a data field for address tag and data field thread id of the first thread referring to a data memory location specified by the address tag, a scratchpad defining a memory buffer for storing internal data of multioperations, the buffer including a single data field for each processor thread, the memory unit configured to access the step cache for a cache search and scratchpad for retrieving and/or storing internal data at different clock cycles and different stages of the processor pipeline during multioperation execution involving data memory reference by the processor.