Patent №
US 10,074,568
Granted
2018-09-11
Filed 2015
Owner
MIE FUJITSU SEMICONDUCTOR LIMITED
Lab
—
AI components
1
hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
14642156
Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced sigma VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.
AI classification
Ownership
MIE FUJITSU SEMICONDUCTOR LIMITED
assignment · 355990150
Assignors
SUVOLTA, INC.
On an employer assignment, the assignors are typically the inventors.