Patent №
US 10,102,149
Granted
2018-10-16
Filed 2017
Owner
INTEL CORPORATION
Lab
—
AI components
1
hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
15488840
A hybrid hierarchical cache is implemented at the same level in the access pipeline, to get the faster access behavior of a smaller cache and, at the same time, a higher hit rate at lower power for a larger cache, in some embodiments. A split cache at the same level in the access pipeline includes two caches that work together. In the hybrid, split, low level cache (e.g., L1) evictions are coordinated locally between the two L1 portions, and on a miss to both L1 portions, a line is allocated from a larger L2 cache to the smallest L1 cache.
AI classification
Ownership
INTEL CORPORATION
assignment · 426600013
Assignors
APPU, ABHISHEK R., RAY, JOYDEEP, VALERIO, JAMES A., KOKER, ALTUG, SURTI, PRASOONKUMAR, VEMBU, BALAJI, FU, WENYIN, BOROLE, BHUSHAN M., SINHA, KAMAL
On an employer assignment, the assignors are typically the inventors.