SELF-ORGANIZED CRITICAL CMOS CIRCUITS AND METHODS FOR COMPUTATION AND INFORMATION PROCESSING

A circuit that makes use of chaos or self-organized criticality to generate a matrix of bits for computation and information processing. The example embodiment utilizes CMOS circuitry and can solve optimization problems. A plurality of unit cells includes multiple transistors in a lattice formation that set voltages as state variables to other transistor cells. Adjustable bifurcation parameters are utilized to bring the chaotic circuit in and out of the chaotic regime. A processing unit with software are utilized for implanting a problem of interest into the chaotic circuit, while data latches or analog to digital converters provide for reading out the voltages from the chaotic circuit.