INSTRUCTION-OPTIMIZING PROCESSOR WITH BRANCH-COUNT TABLE IN HARDWARE

Patent №

US 10,241,810

Granted

2019-03-26

Filed 2012

Owner

NVIDIA CORPORATION

Lab

NVIDIA AI

AI components

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

13475755

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A processing system comprising a microprocessor core and a translator. Within the microprocessor core is arranged a hardware decoder configured to selectively decode instructions for execution in the microprocessor core, and, a logic structure configured to track usage of the hardware decoder. The translator is operatively coupled to the logic structure and configured to selectively translate the instructions for execution in the microprocessor core, based on the usage of the hardware decoder as determined by the logic structure.

AI hardwareG06F 9/45516G06F 9/30174

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AI classification

AI hardware1.00

Planning0.05

Evolutionary computation0.03

Natural language0.03

Machine learning0.02

Knowledge representation0.01

Vision0.00

Speech0.00

Ownership

NVIDIA CORPORATION

assignment · 288310565

Assignors

BRAUCH, RUPERT, SWARNA, MADHU, SEGELKEN, ROSS, DUNN, DAVID, HERTZBERG, BEN

On an employer assignment, the assignors are typically the inventors.

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Cites (64)

TRANSLATION LOOKASIDE BUFFER ENTRY SYSTEMS AND METHODSUS 9,547,602 · 2017 CUSTOM CHAINING STUBS FOR INSTRUCTION CODE TRANSLATIONUS 9,384,001 · 2016 APPARATUS, METHOD, AND SYSTEM FOR PROVIDING A DECISION MECHANISM FOR CONDITIONAL COMMITS IN AN ATOMIC REGIONUS 8,549,504 · 2013 GUARANTEED PREFETCH INSTRUCTIONUS 8,533,437 · 2013 MICROPROCESSOR WITH REPEAT PREFETCH INDIRECT INSTRUCTIONUS 8,364,902 · 2013 APPARATUS AND METHOD FOR HETEROGENEOUS CHIP MULTIPROCESSORS VIA RESOURCE ALLOCATION AND RESTRICTIONUS 8,190,863 · 2012 RUNAHEAD EXECUTION FOR GRAPHICS PROCESSING UNITSUS 8,035,648 · 2011 MIGRATING A VIRTUAL MACHINE IN RESPONSE TO FAILURE OF AN INSTRUCTION TO EXECUTEUS 7,925,923 · 2011 APPARATUS AND METHOD FOR SECURE HASH ALGORITHMUS 7,921,300 · 2011 MULTI-THREADING PROCESSORS, INTEGRATED CIRCUIT DEVICES, SYSTEMS, AND PROCESSES OF OPERATION AND MANUFACTUREUS 7,890,735 · 2011 SUPPORTING SPECULATIVE MODIFICATION IN A DATA CACHEUS 7,873,793 · 2011 LEAKY-BUCKET THREAD SCHEDULER IN A MULTITHREADING MICROPROCESSORUS 7,752,627 · 2010 HORIZONTALLY SCALABLE AND RELIABLE DISTRIBUTED TRANSACTION MANAGEMENT IN A CLUSTERED APPLICATION SERVER ENVIRONMENTUS 7,730,489 · 2010 DETERMINING MEMORY CONDITIONS IN A VIRTUAL MACHINEUS 7,702,843 · 2010 APPARATUS, SYSTEM, AND METHOD FOR USING PAGE TABLE ENTRIES IN A GRAPHICS SYSTEM TO PROVIDE STORAGE FORMAT INFORMATION FOR ADDRESS TRANSLATIONUS 7,545,382 · 2009 PHYSICALLY-BASED PAGE CHARACTERIZATION DATAUS 7,519,781 · 2009 METHOD AND APPARATUS FOR FRAGMENT PROCESSING IN A VIRTUAL MEMORY SYSTEMUS 7,447,869 · 2008 DATA PROCESSING SYSTEM HAVING AN EXTERNAL INSTRUCTION SET AND AN INTERNAL INSTRUCTION SETUS 7,406,585 · 2008 BRANCH BASED ACTIVITY MONITORINGUS 7,340,628 · 2008 ACROSS-THREAD OUT OF ORDER INSTRUCTION DISPATCH IN A MULTITHREADED GRAPHICS PROCESSORUS 7,310,722 · 2007 EXECUTING PROGRAMS FOR A FIRST COMPUTER ARCHITECTURE ON A COMPUTER OF A SECOND ARCHITECTUREUS 7,275,246 · 2007 PAGE MAPPING COOKIESUS 7,234,038 · 2007 METHOD AND SYSTEM FOR USING IDIOM RECOGNITION DURING A SOFTWARE TRANSLATION PROCESSUS 7,203,932 · 2007 ADDRESS GENERATION INTERLOCK RESOLUTION UNDER RUNAHEAD EXECUTIONUS 7,194,604 · 2007 MECHANISM FOR PROCESSOR POWER STATE AWARE DISTRIBUTION OF LOWEST PRIORITY INTERRUPTUS 7,191,349 · 2007

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