STORAGE MEDIUM STORING CACHE MISS ESTIMATION PROGRAM, CACHE MISS ESTIMATION METHOD, AND INFORMATION PROCESSING APPARATUS

Patent №

US 10,366,015

Granted

2019-07-30

Filed 2017

Owner

FUJITSU LIMITED

Lab

AI components

3

kr · evo · hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

15498666

A method for a cache miss estimation includes; generating a variable range of a possible value of loop variables relevant to a specific array; generating first expression of number of times indicating the number of times the specific position of a specific loop is executed; generating second expression of number of times indicating the number of times the data of the access target is stored in the cache; generating third expression of number of times indicating the number of times the data of the access target is removed from the cache; generating fourth expression of number of times, from a generated conflict miss cause common expression, indicating the number of times the data of the access target is stored in the cache; and estimating a number of cache miss based on the difference between the first and the second expressions and the difference between the third and the forth expressions.

Knowledge representationEvolutionary computationAI hardwareG06F 12/128G06F 11/34G06F 11/3409G06F 11/3466G06F 12/0868G06F 2201/885G06F 2212/225

AI classification

AI hardware1.00
Knowledge representation0.99
Evolutionary computation0.77
Natural language0.02
Vision0.01
Machine learning0.00
Planning0.00
Speech0.00

Ownership

FUJITSU LIMITED

assignment · 421940610

Assignors

ARAI, MASAKI

On an employer assignment, the assignors are typically the inventors.

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