MULTI-CHIP TOUCH ARCHITECTURE FOR SCALABILITY

A multi-chip touch architecture for scalability can include one or more touch controller application specific integrated circuits (ASICs), and one or more switching circuits coupled between the one or more touch controller ASICs and the touch sensor panel. The number of touch controller ASICs and switching circuits can be scaled based on the size of the touch sensor panel. The touch controller ASICs can include an interface for data transfer between the touch controller ASICs to allow for parallel processing of an image of touch by more than one touch controller ASIC. The touch controller ASIC can also include a memory directly accessible by more than one processing circuit (e.g., hardware accelerators), and circuitry to dynamically adjust the coupling between portions (e.g., banks) of memory and inputs of the one or more processing circuits to minimize data transfer and improve processing speeds.