LATENCY SCHEDULING MECHANISM

Patent №

US 10,691,430

Granted

2020-06-23

Filed 2018

Owner

INTEL CORPORATION

Lab

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

16113650

An apparatus to facilitate instruction scheduling is disclosed. The apparatus includes one or more processors to receive a block of instructions, divide the block of instructions into a plurality of sub-blocks based on a register pressure bounded by a predetermined threshold and instructions in each of the plurality of sub-blocks for processing.

AI hardwareG06F 8/41G06F 8/445G06F 9/30101G06F 9/4552G06T 1/20G06T 1/60G06T 15/005G06T 15/04+2 more

AI classification

AI hardware0.99
Natural language0.02
Planning0.01
Knowledge representation0.00
Evolutionary computation0.00
Machine learning0.00
Speech0.00
Vision0.00

Ownership

INTEL CORPORATION

assignment · 467140061

Assignors

PAN, WEI, CHEN, WEI-YU, LUEH, GUEI-YUAN

On an employer assignment, the assignors are typically the inventors.

From the same owner

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