HARDWARE ACCELERATOR FOR COMPRESSED RNN ON FPGA

Patent №

US 10,698,657

Granted

2020-06-30

Filed 2016

Owner

BEIJING DEEPHI INTELLIGENCE TECHNOLOGY CO., LTD.

+3 more

Lab

—

AI components

ml · hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

15390563

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The present invention relates to recurrent neural network. In particular, the present invention relates to how to implement and accelerate a recurrent neural network based on an embedded FPGA. Specifically, it proposes an overall design processing method of matrix decoding, matrix-vector multiplication, vector accumulation and activation function. In another aspect, the present invention proposes an overall hardware design to implement and accelerate the above process.

Machine learning AI hardwareG06F 7/501G06F 7/523G06F 7/5443G06N 3/044G06N 3/0442G06N 3/0495G06N 3/063G06F 2207/4824

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AI classification

Machine learning1.00

AI hardware1.00

Planning0.33

Vision0.04

Natural language0.01

Knowledge representation0.00

Speech0.00

Evolutionary computation0.00

Ownership

BEIJING DEEPHI INTELLIGENCE TECHNOLOGY CO., LTD.

assignment · 407770420

BEIJING DEEPHI INTELLIGENT TECHNOLOGY CO., LTD.

correct · 455290239

BEIJING DEEPHI TECHNOLOGY CO., LTD.

correct · 455290400

XILINX, INC.

assignment · 503770436

Assignors

KANG, JUNLONG, HAN, SONG, SHAN, YI

On an employer assignment, the assignors are typically the inventors.

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Cites (1)

UNIVERSAL FPGA/ASIC MATRIX-VECTOR MULTIPLICATION ARCHITECTUREUS 9,317,482 · 2016

Cited by (9)

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