METHOD AND SYSTEM FOR GENERATING A VALIDATION TEST

A method for generating a validation test for testing an electronic design may include using a processor, analyzing a plurality of actions of a validated scenario to identify an executable corresponding to each of the actions and to identify one or a plurality of variables referred to by each of the actions; using a processor, identifying actions in said plurality of actions that correspond to different executables of the identified executables but refer to a same variable of said one or a plurality of variables that is to be written to or read from a shared memory assigned to the different executables; and using a processor, generating a test code for the validated scenario that includes one or a plurality of access protection commands to manage access by the identified actions that correspond to the different executables and refer to the same variable.