Patent US 11,006,288

An automated highly efficient “design-test-optimize” recursive loop method for experimentally optimizing embedding networks of active RF networks especially subject to wideband modulated signals, whereby the results of a matching network design are fed into the active load pull system, which synthesizes the response of the specific network design iteration and tests the transistor in real time under the emulated load conditions of the network. The weighed difference between expected and test results are used in an error function and the “design-test” loop is repeated until the error is minimized. The capacity of passive and active modulated tuners and network analysis software tools are jointly used, sharing calculated and measured data. The result of the automated optimization procedure ends into a compromise, which, if acceptable, can be processed into manufacturing with realistically expectable results.