PARALLEL FAULT SIMULATOR WITH BACK PROPAGATION ENHANCEMENT

This application discloses a computing system implementing a functional safety validation tool to simulate an integrated circuit design with a stimulus vector. The computing system can inject a fault at a first node of the simulated integrated circuit design, which prompts alarm logic to trigger indicating a detection of the injected fault. The computing system, in response to the triggering of the alarm logic, can initiate back-propagation to identify which intermediate nodes of the simulated integrated circuit design, located between the first node and the alarm logic, have fault values that prompt the alarm logic to trigger. The computing system can generate a fault coverage presentation identifying a diagnostic coverage of the alarm logic for the stimulus vector based on when the alarm logic.