Power Management For An Analog Neural Memory In A Deep Learning Artificial Neural Network

Patent №

US 11,409,352

Granted

2022-08-09

Filed 2019

Owner

SILICON STORAGE TECHNOLOGY, INC.

Lab

—

AI components

ml · hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

16354040

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Numerous embodiments of power management techniques are disclosed for various operations involving one or more vector-by-matrix multiplication (VMM) arrays within an artificial neural network.

Machine learning AI hardwareG06F 1/3234G06F 1/3203G06F 17/16G06N 3/04G06N 3/044G06N 3/0442G06N 3/0464G06N 3/065+5 more

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AI classification

AI hardware1.00

Machine learning1.00

Evolutionary computation0.18

Knowledge representation0.09

Speech0.03

Natural language0.00

Planning0.00

Vision0.00

Ownership

SILICON STORAGE TECHNOLOGY, INC.

assignment · 492120490

Assignors

TRAN, HIEU VAN, TIWARI, VIPIN, REITEN, MARK, DO, NHAN

On an employer assignment, the assignors are typically the inventors.

From the same owner

VERIFICATION METHOD AND SYSTEM IN ARTIFICIAL NEURAL NETWORK ARRAYUS 12,694,070 · 2026 PRECISION TUNING FOR THE PROGRAMMING OF ANALOG NEURAL MEMORY IN A DEEP LEARNING ARTIFICIAL NEURAL NETWORKUS 12,694,279 · 2026 VECTOR-BY-MATRIX-MULTIPLICATION ARRAY UTILIZING ANALOG OUTPUTSUS 12,670,228 · 2026 Testing Circuitry And Methods For Analog Neural Memory In Artificial Neural NetworkUS 12,670,376 · 2026 ADJUSTABLE PROGRAMMING CIRCUIT FOR NEURAL NETWORKUS 12,670,377 · 2026 ULTRA-PRECISE TUNING OF NEURAL MEMORY CELLSUS 12,665,028 · 2026 OUTPUT CIRCUIT FOR ANALOG NEURAL MEMORY IN A DEEP LEARNING ARTIFICIAL NEURAL NETWORKUS 12,639,001 · 2026 CALIBRATION OF ELECTRICAL PARAMETERS IN A DEEP LEARNING ARTIFICIAL NEURAL NETWORKUS 12,639,559 · 2026

Cites (24)

RESISTIVE PROCESSING UNITS WITH COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR NON-VOLATILE ANALOG MEMORYUS 10,741,611 · 2020 UNIT CELL WITH FLOATING GATE MOSFET FOR ANALOG MEMORYUS 10,217,512 · 2019 SEMICONDUCTOR MEMORY ARRAY OF FLOATING GATE MEMORY CELLS WITH PROGRAM/ERASE AND SELECT GATESUS 7,315,056 · 2008 FLASH MEMORY CELLS WITH SEPARATED SELF-ALIGNED SELECT AND ERASE GATES, AND PROCESS OF FABRICATIONUS 6,747,310 · 2004 NEURAL PROCESSING MODULE WITH INPUT ARCHITECTURES THAT MAKE MAXIMAL USE OF A WEIGHTED SYNAPSE ARRAYUS 6,389,404 · 2002 Mixed program and sense architecture using dual-step voltage scheme in multi-level data storage in flash memoriesUS 6,282,119 · 2001 HOLE IMPACT IONIZATION MECHANISM OF HOT ELECTRON INJECTION AND FOUR-TERMINAL P-FET SEMICONDUCTOR STRUCTURE FOR LONG-TERM LEARNINGUS 5,990,512 · 1999 METHOD FOR IMPLEMENTING A LEARNING FUNCTIONUS 5,914,894 · 1999 NEURON CIRCUITUS 5,621,336 · 1997 ONE-TRANSISTOR ADAPTABLE ANALOG STORAGE ELEMENT AND ARRAYUS 5,336,936 · 1994 NONVOLATILE PROGRAMMABLE NEURAL NETWORK SYNAPTIC ARRAYUS 5,298,796 · 1994 DIFFERENCE CALCULATING NEURAL NETWORK UTILIZING SWITCHED CAPACITORSUS 5,264,734 · 1993 NEURAL NETWORK WITH MULTIPLEXED SYNAPTIC PROCESSINGUS 5,256,911 · 1993 METHOD AND CIRCUITS FOR NEURON PERTURBATION IN ARTIFICAL NEURAL NETWORK MEMORY MODIFICATIONUS 5,150,450 · 1992 METHOD OF INCREASING THE ACCURACY OF AN ANALOG NEURAL NETWORK AND THE LIKEUS 5,146,602 · 1992 METHOD AND APPARATUS FOR ERASING AN ARRAY OF ELECTRICALLY ERASABLE EPROM CELLSUS 5,138,576 · 1992 SEMICONDUCTOR CELL FOR NEURAL NETWORK AND THE LIKEUS 5,055,897 · 1991 FOUR QUADRANT SYNAPSE CELL EMPLOYING SINGLE COLUMN SUMMING LINEUS 5,028,810 · 1991 SINGLE TRANSISTOR NON-VOLATILE ELECTRICALLY ALTERABLE SEMICONDUCTOR MEMORY DEVICEUS 5,029,130 · 1991 SYNAPSE CELL EMPLOYING DUAL GATE TRANSISTOR STRUCTUREUS 4,961,002 · 1990 SEMICONDUCTOR CELL FOR NEURAL NETWORK EMPLOYING A FOUR-QUADRANT MULTIPLIERUS 4,950,917 · 1990 EXCLUSIVE-OR CELL FOR NEURAL NETWORK AND THE LIKEUS 4,904,881 · 1990 Patent US 5,509,106US 5,509,106 Patent US 6,829,598US 6,829,598

Cited by (1)

MEMORY COMPUTATION CIRCUITUS 11,830,543 · 2023

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