POST SIMULATION DEBUG AND ANALYSIS USING A SYSTEM MEMORY MODEL

Patent №

US 11,487,561

Granted

2022-11-01

Filed 2014

Owner

CADENCE DESIGN SYSTEMS, INC.

Lab

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

14582800

According to an embodiment, a system and method are provided for constructing an accurate view of memory and events on a simulation platform. The system memory view can be used with a debug and analysis tool to provide post-processing debug, including searching forward and backward in capture time of the stored memory view to analyze the events of the simulation. The memory is constructed by capturing and storing each memory execution transaction, bus transaction, and register transaction during simulation. Changes in simulation platform hardware state may also be captured and stored in a hardware state database, including switches between process threads detected during the simulation that may update a simulator register. The captured events provide observability into the OS processes, the hardware, and the embedded software of the simulation platform.

AI hardwareG06F 9/455G06F 11/3636G06F 11/364G06F 11/3698G06F 16/245

AI classification

AI hardware1.00
Knowledge representation0.01
Natural language0.01
Planning0.00
Evolutionary computation0.00
Machine learning0.00
Vision0.00
Speech0.00

Ownership

CADENCE DESIGN SYSTEMS, INC.

assignment · 345840884

Assignors

WILMOT, ANDREW, BHATNAGAR, NEETI KHULLAR, CHAO, QIZHANG, FRAZIER, GEORGE FRANKLIN

On an employer assignment, the assignors are typically the inventors.

From the same owner

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