COMPUTE-IN-MEMORY (CIM) BIT CELL CIRCUITS EACH DISPOSED IN AN ORIENTATION OF A CIM BIT CELL CIRCUIT LAYOUT INCLUDING A READ WORD LINE (RWL) CIRCUIT IN A CIM BIT CELL ARRAY CIRCUIT

Compute-in-memory (CIM) bit cell array circuits include CIM bit cell circuits for multiply-accumulate operations. The CIM bit cell circuits include a memory bit cell circuit for storing a weight data in true and complement form. The CIM bit cell circuits include a true pass-gate circuit and a complement pass-gate circuit for generating a binary product of the weight data and an activation input on a product node. An RWL circuit couples the product node to a ground voltage for initialization. The CIM bit cell circuits also include a plurality of consecutive gates each coupled to at least one of the memory bit cell circuit, the true pass-gate circuit, the complement pass-gate circuit, and the RWL circuit. Each of the CIM bit cell circuits in the CIM bit cell array circuit is disposed in an orientation of a CIM bit cell circuit layout including the RWL circuit.