PERFORMANCE TUNING OF A HARDWARE DESCRIPTION LANGUAGE SIMULATOR

Some aspects of this disclosure are directed automated performance tuning of a hardware description language (HDL) simulation system. For example, some aspects of this disclosure relate to a method, including generating, by a first subsystem optimizer, a plurality of recommendations corresponding to a first subsystem of a hardware description language (HDL) simulation system. The plurality of recommendations are generated by the first subsystem optimizer using one or more optimization applications. The method further includes generating, by the first subsystem optimizer, a first aggregate recommendation by combining the plurality of recommendations corresponding to the first subsystem of the HDL simulation system. The method further includes updating a configuration of the first subsystem of the HDL simulation system based on the first aggregate recommendation, wherein the HDL simulation system is configured to simulate a circuit design using the updated configuration during execution of the first subsystem.