A METHOD FOR VALIDATING A HARDWARE SYSTEM

Disclosed is a method for validating a hardware system by a model thereof, which method comprises: providing reference structures and determining, in the model, sub-structures, each of which is structurally equivalent to one of the reference structures; extracting, from the model, input cones for each sub-structure; creating monopartite candidate graphs by mapping the bipartite sub-structure and the respective input cones to one of the candidate graphs; creating, for each candidate graph, a match vector, each dimension of the match vector comprising a count of occurrences, in the candidate graph, of a different one of predetermined graphlets; clustering, on the basis of similarity of the match vectors, the candidate graphs in clusters; and selecting, from each of the clusters, one candidate graph and determining a functional behaviour of the respective sub-structure of the selected candidate graph for validating the hardware system.