Patent №
US 11,675,956
Granted
2023-06-13
Filed 2021
Owner
CADENCE DESIGN SYSTEMS, INC.
Lab
—
AI components
1
planning
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
17219748
A system includes a machine configured to perform operations including accessing an integrated circuit design including a buffer tree that interconnects a plurality of inputs and buffers. The buffer tree includes a baseline timing characteristic. The operations include identifying a set of candidate solutions for improving the baseline timing characteristic using an initial timing model and selecting a subset of candidate solutions that have a timing characteristic lower than the baseline timing characteristic. Then the subset of candidate solutions are evaluated using a detailed timing model and based on determining that at least one candidate solution in the subset has a timing characteristic that is better than the baseline timing characteristic, selecting a candidate solution from the set of candidate solutions, and updating the buffer tree based on the candidate solution.
AI classification
Ownership
CADENCE DESIGN SYSTEMS, INC.
assignment · 601970340
Assignors
GAO, JHIH-RONG, DING, YI-XIAO, LI, ZHUO
On an employer assignment, the assignors are typically the inventors.