SELF-REFERENCED DELAY CELL-BASED TIME-TO-DIGITAL CONVERTER

A time-to-digital converter (TDC) circuit includes control logic and a first self-referenced delay cell circuit coupled to the control logic. The first self-referenced delay cell circuit includes: a first bank of capacitors coupled to a first node between a first positive input and a first positive output, where the first bank of capacitors is selectively controlled by a first control signal from the control logic, the first control signal including a first up value corresponding to a first positive threshold; and a second bank of capacitors coupled to a second node between a first negative input and a first negative output, where the second bank of capacitors is selectively controlled by a second control signal from the control logic, the second control signal including a first down value corresponding to a first negative threshold.