DIE YIELD ASSESSMENT BASED ON PATTERN-FAILURE RATE SIMULATION

This application discloses a computing system to identify structures of an integrated circuit capable of being fabricated utilizing a lithographic mask described by mask layout data and to generate process windows for the identified structures based, at least in part, on the mask layout data and a failure definition for the identified structures. The computing system utilizes process windows for the identified structures to determine failure rates for the identified structures based on a distribution of the manufacturing parameters. The computing system determines frequency of occurrences for the identified structures from the mask layout data and generates a die yield metric for the integrated circuit by aggregating the failure rates for the identified structures based on the frequency of occurrences for the identified structures in the integrated circuit. These increases in yield of the integrated circuit allow manufacturers to produce more units per fixed processing cost of the wafer.