Compile Time Instrumentation of Data Flow Graphs

Patent №

US 11,782,856

Granted

2023-10-10

Filed 2021

Owner

SAMBANOVA SYSTEMS, INC.

Lab

AI components

3

kr · planning · hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

17479861

A data processing system comprises memory, compile time logic, runtime logic, and instrumentation profiling logic. The memory stores a dataflow graph for an application. The dataflow graph has a plurality of compute nodes that are configured to be producers to produce data for execution of the application, and to be consumers to consume the data for execution of the application. The compile time logic partitions execution of the dataflow graph into stages. Each of the stages has one or more compute nodes, one or more producers, and one or more consumers. The runtime logic determines a processing latency for each of the stages by calculating time elapsed between producers of a particular stage receiving input data and consumers of the particular stage receiving output data. The instrumentation profiling logic generates performance statistics for the dataflow graph based on the processing latency determined for each of the stages.

Knowledge representationPlanningAI hardwareG06F 13/20G06F 15/7871G06F 8/433G06F 9/4494G06F 11/302G06F 11/3419G06F 11/3452G06F 11/3466+3 more

AI classification

Knowledge representation0.99
AI hardware0.84
Planning0.65
Machine learning0.01
Natural language0.00
Evolutionary computation0.00
Vision0.00
Speech0.00

Ownership

SAMBANOVA SYSTEMS, INC.

assignment · 592990921

Assignors

PRABHAKAR, RAGHU, GRIMM, MATTHEW THOMAS, JAIRATH, SUMTI, LEUNG, KIN HING, GUPTA, SITANSHU, LIN, YUAN, BOASSO, LUCA

On an employer assignment, the assignors are typically the inventors.

© 2026 NYSGPT2525 LLC