Patent US 3,941,990

Series type adder receiving numbers having different polarities, constituted by elementary series type adders combining the positive input numbers and the true complements of the negative input numbers to work out the sum .SIGMA. thereof, characterized in that it comprises means for calculating the sum S of the sign bits of the negative input numbers and effecting the storing thereof in a memory, means for extracting the exceeding number D appearing at the end of the calculating of .SIGMA., means for comparing S and D in order to determine the sign of .SIGMA. existing in a memory register and in order to control the transferring thereof in true form, in an output, preceded by its sign.