Patent US 3,944,801

A device is provided for the exact automatic computation of sales tax rather than calculation of tax as a percentage. In the disclosure, a first subset of tax cutoff values and a second subset of repeating increments of values, corresponding to repeating increments of tax, are stored in a memory. The amount on which the tax is to be calculated is entered into a register and compared in a CPU to the total vlaue of the first subset. The CPU provides a zero output to a register when the amount is less than the first subset. When the amount is larger, the CPU subtracts the first subset from the amount. A divider in the CPU divides the remainder by the total value of the second subset. A multiplier multiplies the whole number quotient, of the division, by a tax amount. The resultant is entered into a register. A comparer and related circuitry compares the quotiant to a first and successive increments in the second subset until a successive one of the increments exceeds the remainder and stores the incremental tax values. In response to the exceeding increment, the CPU terminates the comparing operation and causes the device to indicate the stored, exact tax value.