Patent US 3,944,975

A signal checking system for use in a hardware system having a converter for converting coded input signals consisting of a plurality of bits into corresponding individual signals, wherein undesirable selection of an erroneous output and multiple outputs by the converter is detected by means adapted for checking the relation between the input to the converter and the output of a first coder connected to the converter and checking the complementary relation between the output of the first coder and the output of a second coder connected to the converter.