Patent US 3,961,750

A parallel shifter consists of a plurality of AND gates arranged in a skewed configuration to simulate the partial products of a multiplication of the binary number to be shifted with a second binary number representing 2.sup.N where N is the number of shift steps. Pseudo multiplication may be accomplished merely by ORing the outputs of the AND gates of any given binary weight since only one partial product of that weight will be non-zero. Left or right shift is accomplished by selection of the most significant or least significant half of the product. Rotation is accomplished by merging of the two halves.