Patent US 3,970,993

A "cooperative-word" linear array parallel processor comprises many logically identical memory words or micro-processors ordered in a linear array by a Chaining channel. Inasmuch as the Chaining channel can contain different information (either data to be processed or control information) at each word position, it permits highly parallel word-cooperative operations such as pair-wise arithmetic. The processor also has several global communication channels in which data may be transferred between an external buffer and a specified subset of processor words. Inasmuch as individual words may be addressed by their content rather than by their physical locations, relatively simple switching logic within each word provides effective self-repair. A plurality of flag flip-flops in each individual cell interact with gobal control lines to activate processing within a particular cell and to indicate the results of operations performed by that cell. Flag data can be passed from one word to another by means of the chaining channel, or they can be manipulated within a word by means of the aforesaid global control lines.