Patent №
US 3,972,024
Granted
1976-07-27
Filed 1974
Owner
—
Lab
—
AI components
1
hardware
Assignment
None on record
Dataset
AIPD
2023_r1 edition
Application
05455060
An improved microinstruction memory addressing method and apparatus within a serial-bit microinstruction processor incorporating internal, serial-byte transfer, is provided by addition to and alteration of memory control circuitry wherein the resulting permissible microinstruction set for controlling the processor may be expanded to include a CALL, GO-TO and EXECUTE operations, thus increasing the programmatic capabilities in the processor. The micro-code needed to define more complicated program operations, and thus the time used to perform these operations, may therefore be greatly reduced. Changes may also be made in existing timing circuitry.