Patent US 3,974,451

An asynchronous receiver system for remotely controlling an apparatus and capable of being substantially completely constructed on a single integrated circuit chip. This system includes an input stage means for receiving during successive receiving cycles an incoming signal comprising repetitive groups of serially received frequency bursts. Each burst is composed of one of a plurality of frequencies and the frequency of the incoming signal lies between harmonic frequencies of interfering signals. A frequency divider means sequentially generates a plurality of localizer frequencies at a first output terminal and a plurality of timing signals at a second plurality of output terminals. Each timing signal is associated with one of the plurality of localizer frequencies. A mixer receives inputs from the input stage and from the first output terminal and generates sum and difference signals in response to the incoming signal and to the plurality of localizer frequencies. A detector is coupled to the mixer and transmits signals of a selected frequency and amplitude range. A gating means is coupled to the detector and to the second plurality of output terminals. Each gating means is responsive to one of the plurality of timing signals and generates during successive receiving cycles successive groups of digital signals. Each of these digital signals represents one of the plurality of received frequency bursts. A memory means is coupled to the gating means and stores the digital signals. An error checking circuit is coupled to the output of the memory means and compares successive groups of digital signals in order to provide error-free operation.