Patent US 3,984,643

A pair of interchangeable memories is provided, one of which receives a PCM frame while simultaneously transmitting one, while the other of which, containing the previous frame, outputs the channel bits for parallel processing. Each simultaneous conference is assigned a temporary storage location in which the associated channels are accumulated to yield the total conference signal. Subsequently, each channel is subtracted from its conference total to produce the final conference signal. The final conference signals replace the unprocessed frame in the memory where, at the end of the current frame, it is interchanged with the other memory. And so on.