Patent US 3,988,596

A voltage memory device is disclosed wherein the gate of a MOS field-effect transistor is connected to one terminal of a capacitor and to an input voltage terminal through an input resistor and through the contacts of a reed relay while the source is connected to an output terminal and an output resistor, the input resistor being inserted in order to determine the charging time of the capacitor. When the reed relay is actuated, the capacitor is charged or discharged depending upon whether the input voltage terminal is connected to a positive or negative voltage supply source so that the output voltage increases or decreases. When the reed relay is de-energized, the output voltage remains at the same level. The voltage memory device has a function similar to that of the conventional variable resistors, but it eliminates the use of any sliding part and is operable at a relatively low voltage in a reliable and dependable manner. The voltage memory may be used in an automatic control system.