Patent US 4,028,679

A read only memory (ROM) patching arrangement is disclosed for providing valid output information whenever defective ROM word locations containing invalid information are addressed. The disclosed arrangement, which includes a decoder comprising a plurality of small capacity PROMs, detects the receipt of each address word representing a defective location, temporarily inhibits the output of the ROM, and causes a small auxiliary memory to output valid information as a substitute for that in the defective ROM location. The patching capability of the auxiliary memory and the decoder PROMs is increased by extending n bits of each ROM address word to n inputs of the auxiliary memory as well as to n inputs of each decoder PROM. The remaining inputs of the decoder PROMs, taken collectively, each receive a different one of the remaining bits of each ROM address.