Patent US 4,044,337

An instruction retry mechanism for enabling a digital data processing system having main, buffer and local stores to restart and, in most cases, recover from an error or failure in the processor hardware associated with the buffer and local stores. A first copy storage mechanism is provided for temporarily storing copies of data written into the local store. Two separately addressable multibit copy storage locations are provided for each local store address. One is capable of holding a copy of the latest data written into a given local store address during the most recent machine instruction cycle involving such address, and the other is capable of holding a copy of the latest data written into the same local store address during the next most recent machine instruction cycle involving such address. A second copy storage mechanism is provided for temporarily storing copies of data written into the buffer store by the instruction processing or instruction execution portion of the system. The storage capacity for this second copy mechanism is substantially smaller than the storage capacity of the buffer store. When the copy store becomes nearly full, room is made for new copies by causing the buffer store to copy back to the main store some of the modified data in the buffer store. This enables new buffer store data to be copied into the copy store in place of the data copied back to the main store without harm to the retry capability of the system. Three separately addressable multibit copy storage locations are provided for each buffer store address having a data copy in the copy store. One is capable of holding a copy of the latest data written into a given buffer store address during the most recent machine instruction cycle involving such address, and another is capable of holding a copy of the latest data written into the same buffer storage address during the next most recent machine instruction cycle involving such data. The third location is used to store a copy of the buffer store address and the main store address for the data Upon occurrence of a machine check interrupt or other error condition necessitating an instruction retry, all the copy data and address information in both copy storage mechanisms is transferred to a separate service processor which controls the retry operation. The service processor restores the data in the system to the condition which existed at the end of the machine instruction immediately preceding the instruction cycle during which the failure occurred. The service processor then instructs the system to repeat the instruction during which the failure occurred. Because two data copy locations are provided for each local store or buffer store address and because these two locations are used during different machine instruction cycles, one of them will, in most cases, include the proper copy for restoring the system to the condition existing at the start of the defective cycle.